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Senior ASIC Design Engineer Full time / Salary basis
Location:
San Jose, CA
Description:
Senior ASIC Design EngineerFull time direct hire/ Salary basis Please send anyone with CPU/ARM/RISC/MIPS experience.They will interview almost anyone with that experience and are in the San Jose area but are open to 100% remote, although the preference is local San Jose, CAAbout Recogni: Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Recogni is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Recogni is a well funded, fast-paced startup company with headquarters in both San Jose, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment. About the role: As a senior member of Recogni?s ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company?s flagship perception module product for autonomous driving applications.This ASIC?s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power.Your responsibilities will be wide-ranging and run the gamut of microarchitecture design and documentation, Verilog RTL implementation, selecting and integration 3rd-party IP blocks, working closely with design verification engineers, running frontend synthesis and working with a backend team on place-and-route guidance and timing closure. Responsibilities:Author micro-architecture specifications and participate in specification and test plan reviews.Architect and implement complex RTL designs.Scope third party IP requirements and solicit vendors.Integrate CPU and other relevant IPs into the CPU sub-system.Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.Analyze code coverage and provide feedback to the verification team to achieve coverage closure.Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab.Required Qualifications: 5+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.Experience in IP integration, specifically CPU IP into SoC.Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operationFamiliarity with AMBA/APB/AXI ProtocolFamiliarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2CHands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domainsPrevious experience with timing closure at high frequencies is a plus.Interest to explore AI architectures for convolution, transformer and other kinds of workloadsSelf-starter and highly-motivated to work in a dynamic start-up environment.B.S. (M.S. preferred) degree in Electrical or Computer engineering. Reasons to consider joining Recogni:Ground floor opportunity with the team; be part of shaping one of the most exciting new companies.Learning and development opportunities from a highly diverse and talented peer group, including experts in a wide range of fields, from Artificial Intelligence & Computer Vision to Systems & Device Engineering.Competitive benefits package including Medical, Vision, DentalPerks including meals, snacks, drinks and us!Sharp, motivated co-workers in a fun office environmentEmployee Stock Purchase PlanFlexible work hours & generous PTO policy Recogni's culture was built on the following values that are equally important to us as business:Put people first. We only succeed when our people succeed.Ethics and integrity always; Being open, honest, and respectful of everyone.Think Big. Be ambitious and have audacious goals.Aim for excellence. Quality and excellence count in everything we do.Own it and get it done. Results matter!Make Each Person Better together than they would be as an individual.Embrace each others? differences.Embrace that there will be differences.
Company:
Stellent IT
Posted:
May 17 on PostJobFree
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More About this Listing: Senior ASIC Design Engineer Full time / Salary basis
Senior ASIC Design Engineer Full time / Salary basis is a Engineering Design Engineer Job at Stellent IT located in San Jose CA. Find other listings like Senior ASIC Design Engineer Full time / Salary basis by searching Oodle for Engineering Design Engineer Jobs.
Senior ASIC Design Engineer Full time / Salary basis is a Engineering Design Engineer Job at Stellent IT located in San Jose CA. Find other listings like Senior ASIC Design Engineer Full time / Salary basis by searching Oodle for Engineering Design Engineer Jobs.